In order to access the registers of the HW, we need to make sure that
the AXI bus clock is enabled.
In order to keep backward compatibility, the new axi clock must be the
last phandle in clocks. On top of that, it's not an actual parent of
the axi-clkgen that needs to be set on struct clk_init_data.
---
Nuno Sa (2):
dt-bindings: clock: axi-clkgen: include AXI clk
clk: clk-axi-clkgen: make sure to enable the AXI bus clock
.../devicetree/bindings/clock/adi,axi-clkgen.yaml | 21 ++++++++++---
drivers/clk/clk-axi-clkgen.c | 35 +++++++++++++++++++++-
2 files changed, 51 insertions(+), 5 deletions(-)
---
base-commit: 94be1620fb60ea542170779915917443cda9bba7
change-id: 20241021-axi-clkgen-fix-axiclk-d1d80bcb9ee1
--
Thanks!
- Nuno Sá
