On Sun, Oct 20, 2024 at 07:40:17PM +0000, Lothar Rubusch wrote: > Convert content of the altera socfpga.txt to match clock bindings for > the Arria10 SoC devicetrees. Currently all altr,* bindings appear as > error at dtbs_check, since these bindings are only written in .txt > format. > Please use subject prefixes matching the subsystem. You can get them for example with 'git log --oneline -- DIRECTORY_OR_FILE' on the directory your patch is touching. For bindings, the preferred subjects are explained here: https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters > Signed-off-by: Lothar Rubusch <l.rubusch@xxxxxxxxx> > --- > .../bindings/clock/altr,socfpga-a10.yaml | 107 ++++++++++++++++++ > 1 file changed, 107 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml > > diff --git a/Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml b/Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml > new file mode 100644 > index 000000000..795826f53 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml > @@ -0,0 +1,107 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/altr,socfpga-a10.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Device Tree Clock bindings for Altera's SoCFPGA platform This wasn't tested or you have some very, very old dtschema. > + > +maintainers: > + - TODO We should not be taking unmaintained stuff. > + > +description: > + This binding uses the common clock binding[1]. > + > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt Drop description or describe the hardware. > + > +properties: > + compatible: > + description: | > + shall be one of the following > + - "altr,socfpga-a10-pll-clock" - for a PLL clock > + - "altr,socfpga-a10-perip-clk" - The peripheral clock divided from the > + PLL clock. > + - "altr,socfpga-a10-gate-clk" - Clocks that directly feed peripherals > + and can get gated. Drop description. > + enum: > + - altr,socfpga-a10-pll-clock > + - altr,socfpga-a10-perip-clk > + - altr,socfpga-a10-gate-clk Why are you adding bindings per clock? Usually that's a no-go, you should be describing here clock controller unit. Best regards, Krzysztof
