On Wed, 09 Oct 2024 14:07:23 +0300, Abel Vesa wrote:
> Fix the description and compatible for PCIe 6a, as it is in fact a
> 4-lanes controller and PHY, but it can also be used in 2-lanes mode. For
> 4-lanes mode, it uses the lanes provided by PCIe 6b. For 2-lanes mode,
> PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. The number
> of lanes in which the PHY should be configured depends on a TCSR register
> value on each individual board.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: qcom: x1e80100: Fix PCIe 6a lanes description
commit: 837c333f46df8ce6755ba82c53acb91948ec0072
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
