On Tue, Oct 8, 2024 at 10:14 AM Billy Tsai <billy_tsai@xxxxxxxxxxxxxx> wrote: > > The Aspeed 7th generation SoC features two GPIO controllers: one with 12 > GPIO pins and another with 216 GPIO pins. The main difference from the > previous generation is that the control logic has been updated to support > per-pin control, allowing each pin to have its own 32-bit register for > configuring value, direction, interrupt type, and more. > This patch serial also add low-level operations (llops) to abstract the > register access for GPIO registers and the coprocessor request/release in > gpio-aspeed.c making it easier to extend the driver to support different > hardware register layouts. > I picked up the first two patches for v6.12. The rest conflicts with my v6.13 branch so I'll send the fixes to Torvalds, wait for rc3 and then apply the rest. Thanks, Bart
