The Aspeed 7th generation SoC features two GPIO controllers: one with 12 GPIO pins and another with 216 GPIO pins. The main difference from the previous generation is that the control logic has been updated to support per-pin control, allowing each pin to have its own 32-bit register for configuring value, direction, interrupt type, and more. This patch serial also add low-level operations (llops) to abstract the register access for GPIO registers and the coprocessor request/release in gpio-aspeed.c making it easier to extend the driver to support different hardware register layouts. Change since v6: - Reorder the patch. - Reoder the llops assignments in the same order as the member declarations. - Add a comment explaining the logic used for the debounce timer array. Change since v5: - Reorder the aspeed_gpio_llops api - Add aspeed_gpio prefix for all of the api - Add mask value check before field_get and field_prep - Separate the devm_clk_get_enabled modification into a new patch. Change since v4: - Add `reg_bank_get` callback - `reg_bits_get` -> `reg_bit_get - `dcache_require` -> `require_dcache` - Use `devm_clk_get_enabled` to get the clock source - g4 specific api doesn't need to use the callback function Change since v3: - Add `privilege_ctrl` and `privilege_init` callback - Use `bool aspeed_gpio_support_copro()` api to replace the `cmd_source_supoort` flag - Add the `dcache_require` flag and move the dcache usage into the reg_bit_set callback - `reg_bits_set` -> `reg_bit_set` and `reg_bits_read` -> `reg_bits_get` - `bool copro = 0` -> `bool copro = false` - `if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bits_get) return -EINVAL;` - Correct the access of reg_irq_status - Remove __init attribute to fix the compiler warning Change since v2: - Correct minItems for gpio-line names - Remove the example for ast2700, because it's the same as the AST2600 - Fix the sparse warning which is reported by the test robot - Remove the version and use the match data to replace it. - Add another two patches one for deferred probe one for flush write. Changes since v1: - Merge the gpio-aspeed-g7.c into the gpio-aspeed.c. - Create the llops in gpio-aspeed.c for flexibility. Billy Tsai (7): gpio: aspeed: Add the flush write to ensure the write complete. gpio: aspeed: Use devm_clk api to manage clock source gpio: aspeed: Change the macro to support deferred probe gpio: aspeed: Remove the name for bank array gpio: aspeed: Create llops to handle hardware access dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700 gpio: aspeed: Support G7 Aspeed gpio controller .../bindings/gpio/aspeed,ast2400-gpio.yaml | 19 +- drivers/gpio/gpio-aspeed.c | 620 +++++++++++------- 2 files changed, 408 insertions(+), 231 deletions(-) -- 2.25.1
