On Tue, Oct 01, 2024 at 10:35:30AM +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx> > > The Inline Crypto Engine (ICE) for UFS/EMMC supports the Hardware Key > Manager (HWKM) to securely manage storage keys. Enable using this > hardware on sm8650. > > This requires us to increase the register range: HWKM is an additional > piece of hardware sitting alongside ICE, and extends the old ICE's > register space. > This commit message doesn't follow what Neil requested in v5: https://lore.kernel.org/lkml/109b1e46-f46f-4636-87d5-66266e04ccff@xxxxxxxxxx/ > Reviewed-by: Om Prakash Singh <quic_omprsing@xxxxxxxxxxx> > Tested-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> I unfortunately can't find where Neil provided this. Is this tag referring to this patch having been tested together with the driver changes, so he's saying that HWKM works fine. Or is he saying that the old feature set still works after the growth of the register region (i.e. what he requested in v5)? Regards, Bjorn > Signed-off-by: Gaurav Kashyap <quic_gaurkash@xxxxxxxxxxx> > Co-developed-by: Gaurav Kashyap <quic_gaurkash@xxxxxxxxxxx> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 01ac3769ffa6..5986a33ddd8b 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -2595,7 +2595,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > ice: crypto@1d88000 { > compatible = "qcom,sm8650-inline-crypto-engine", > "qcom,inline-crypto-engine"; > - reg = <0 0x01d88000 0 0x8000>; > + reg = <0 0x01d88000 0 0x18000>; > > clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > }; > > -- > 2.43.0 > >
