From: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC.
Tested-by: Thomas Bonnefille <thomas.bonnefille@xxxxxxxxxxx>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
Signed-off-by: Drew Fustini <dfustini@xxxxxxxxxxxxxxx>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++
arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++++++++
3 files changed, 32 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index d9b4de9e4757..be85e3aee56e 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -44,6 +44,10 @@ &osc_32k {
clock-frequency = <32768>;
};
+&aonsys_clk {
+ clock-frequency = <73728000>;
+};
+
&apb_clk {
clock-frequency = <62500000>;
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 1365d3a512a3..530648ad64f6 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -25,6 +25,10 @@ &osc_32k {
clock-frequency = <32768>;
};
+&aonsys_clk {
+ clock-frequency = <73728000>;
+};
+
&apb_clk {
clock-frequency = <62500000>;
};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 3c9974062c20..834dcd1fe7d8 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -215,6 +215,12 @@ osc_32k: 32k-oscillator {
#clock-cells = <0>;
};
+ aonsys_clk: aonsys-clk {
+ compatible = "fixed-clock";
+ clock-output-names = "aonsys_clk";
+ #clock-cells = <0>;
+ };
+
apb_clk: apb-clk-clock {
compatible = "fixed-clock";
clock-output-names = "apb_clk";
@@ -357,6 +363,12 @@ portd: gpio-controller@0 {
};
};
+ padctrl1_apsys: pinctrl@ffe7f3c000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xe7f3c000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ };
+
gpio0: gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
@@ -393,6 +405,12 @@ portb: gpio-controller@0 {
};
};
+ padctrl0_apsys: pinctrl@ffec007000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xec007000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ };
+
uart2: serial@ffec010000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
@@ -529,6 +547,12 @@ porte: gpio-controller@0 {
};
};
+ padctrl_aosys: pinctrl@fffff4a000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xfff4a000 0x0 0x2000>;
+ clocks = <&aonsys_clk>;
+ };
+
ao_gpio1: gpio@fffff52000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff52000 0x0 0x1000>;
--
2.34.1
