On Thu, 20 Jun 2024 03:36:21 +0300, Cristian Ciocaltea wrote:
> The HDMI PHY PLL can be used as an alternative clock source to RK3588
> SoC CRU. Since it provides more accurate clock rates, it can be used by
> VOP2 to improve display modes handling, such as supporting non-integer
> refresh rates.
>
> The first two patches in the series provide a couple of fixes and
> improvements to the existing HDPTX PHY driver, while the next two add
> the necessary changes to support the clock provider functionality.
>
> [...]
Applied, thanks!
[1/4] phy: phy-rockchip-samsung-hdptx: Explicitly include pm_runtime.h
commit: 1b369ff94bc36d2e16c8a91c0ea8ebd329555976
[2/4] phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY core level
commit: 10ba8479f460e9256f7d884dc1b7d89006a89c7b
[3/4] dt-bindings: phy: rockchip,rk3588-hdptx-phy: Add #clock-cells
commit: a652f2210054276990d45626a3b9ad5c99465f5a
[4/4] phy: phy-rockchip-samsung-hdptx: Add clock provider support
commit: c4b09c562086f32588d962d30d0b7e93fe3e7cbb
Best regards,
--
Vinod Koul <vkoul@xxxxxxxxxx>
