Add device tree support for Synopsys DesignWare HDMI RX
Controller.
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@xxxxxxxxxxxxx>
Tested-by: Dmitry Osipenko <dmitry.osipenko@xxxxxxxxxxxxx>
Co-developed-by: Dingxian Wen <shawn.wen@xxxxxxxxxxxxxx>
Signed-off-by: Dingxian Wen <shawn.wen@xxxxxxxxxxxxxx>
Signed-off-by: Shreeya Patel <shreeya.patel@xxxxxxxxxxxxx>
---
Changes in v4 :-
- Remove DTS changes added to this patch
- Remove the HDMI RX pin nodes as it's already present
in the rk3588-base-pinctrl.dtsi
Changes in v3 :-
- Rename cma node and phandle names
- Elaborate the comment to explain 160MiB calculation
- Move &hdmi_receiver_cma to the rock5b dts file
Changes in v2 :-
- Fix some of the checkpatch errors and warnings
- Rename resets, vo1-grf and HPD
- Move hdmirx_cma node to the rk3588.dtsi file
.../dts/rockchip/rk3588-base-pinctrl.dtsi | 14 +++++
.../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 56 +++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
index 30db12c4fc82..ca006f5a4c90 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
@@ -594,6 +594,20 @@ hdmim0_tx1_hpd: hdmim0-tx1-hpd {
/* hdmim0_tx1_hpd */
<1 RK_PA6 5 &pcfg_pull_none>;
};
+
+ /omit-if-no-ref/
+ hdmim1_rx: hdmim1-rx {
+ rockchip,pins =
+ /* hdmim1_rx_cec */
+ <3 RK_PD1 5 &pcfg_pull_none>,
+ /* hdmim1_rx_scl */
+ <3 RK_PD2 5 &pcfg_pull_none_smt>,
+ /* hdmim1_rx_sda */
+ <3 RK_PD3 5 &pcfg_pull_none_smt>,
+ /* hdmim1_rx_hpdin */
+ <3 RK_PD4 5 &pcfg_pull_none>;
+ };
+
/omit-if-no-ref/
hdmim1_rx_cec: hdmim1-rx-cec {
rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
index 0ce0934ec6b7..96f8ce91eaf4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -7,6 +7,29 @@
#include "rk3588-extra-pinctrl.dtsi"
/ {
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * The 4k HDMI capture controller works only with 32bit
+ * phys addresses and doesn't support IOMMU. HDMI RX CMA
+ * must be reserved below 4GB.
+ * The size of 160MB was determined as follows:
+ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB
+ * To ensure sufficient support for practical use-cases,
+ * we doubled the 66MB value.
+ */
+ hdmi_receiver_cma: hdmi-receiver-cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
+ size = <0x0 (160 * 0x100000)>; /* 160MiB */
+ no-map;
+ status = "disabled";
+ };
+ };
+
usb_host1_xhci: usb@fc400000 {
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfc400000 0x0 0x400000>;
@@ -135,6 +158,39 @@ i2s10_8ch: i2s@fde00000 {
status = "disabled";
};
+ hdmi_receiver: hdmi_receiver@fdee0000 {
+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
+ reg = <0x0 0xfdee0000 0x0 0x6000>;
+ power-domains = <&power RK3588_PD_VO1>;
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo1-grf = <&vo1_grf>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "cec", "hdmi", "dma";
+ clocks = <&cru ACLK_HDMIRX>,
+ <&cru CLK_HDMIRX_AUD>,
+ <&cru CLK_CR_PARA>,
+ <&cru PCLK_HDMIRX>,
+ <&cru CLK_HDMIRX_REF>,
+ <&cru PCLK_S_HDMIRX>,
+ <&cru HCLK_VO1>;
+ clock-names = "aclk",
+ "audio",
+ "cr_para",
+ "pclk",
+ "ref",
+ "hclk_s_hdmirx",
+ "hclk_vo1";
+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
+ reset-names = "axi", "apb", "ref", "biu";
+ memory-region = <&hdmi_receiver_cma>;
+ pinctrl-0 = <&hdmim1_rx>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
pcie3x4: pcie@fe150000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
--
2.39.2
