Using a combination of fixed clock and gpio-gate clock works but does
not describe the actual hardware. Use the new clock-generator binding
to describe this in a nicer way.
Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
index f870f84da1e6d..4c5be356fa7fe 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
@@ -49,19 +49,14 @@ led-1 {
* 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
* clock generator.
* The clock output is gated via the OE pin on the clock generator.
- * This is modeled as a fixed-clock plus a gpio-gate-clock.
*/
- pcie_refclk_gen: pcie-refclk-gen-clock {
- compatible = "fixed-clock";
+ pcie_refclk: pcie-clock-generator {
+ compatible = "diodes,pi6c557-05b", "clock-generator";
#clock-cells = <0>;
clock-frequency = <100000000>;
- };
-
- pcie_refclk: pcie-refclk-clock {
- compatible = "gpio-gate-clock";
- clocks = <&pcie_refclk_gen>;
- #clock-cells = <0>;
+ clock-output-names = "pcie3_refclk";
enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */
+ vdd-supply = <&vcca_3v3_s0>;
};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
--
2.39.2
