On Fri, Jun 07, 2024 at 02:01:57PM +0200, Martin Schiller wrote: > On 2024-06-07 13:03, Vladimir Oltean wrote: > > On Thu, Jun 06, 2024 at 10:52:23AM +0200, Martin Schiller wrote: > > > From: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > > > > > > Add the CPU port to gswip_xrx200_phylink_get_caps() and > > > gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal > > > bus, > > > so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL. > > > > > > Signed-off-by: Martin Blumenstingl > > > <martin.blumenstingl@xxxxxxxxxxxxxx> > > > --- > > > > This is for the case where those CPU port device tree properties are > > present, right? In the device trees in current circulation they are not, > > and DSA skips phylink registration. > > Yes, as far as I know, this driver is mainly, if not exclusively, used in > the > openWrt environment. These functions were already added here in Oct. 2022 > [1]. > > [1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=2683cca5927844594f7835aa983e2690d1e343c6 Ok. You can add my Reviewed-by: Vladimir Oltean <olteanv@xxxxxxxxx>
