On Thu, Jun 06, 2024 at 10:52:23AM +0200, Martin Schiller wrote: > From: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > > Add the CPU port to gswip_xrx200_phylink_get_caps() and > gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal bus, > so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > --- This is for the case where those CPU port device tree properties are present, right? In the device trees in current circulation they are not, and DSA skips phylink registration.
