On 04/06/2024 11:52, Siddharth Vadapalli wrote: > J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one > instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane > SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller. > > Since SERDES and PCIe are not present on AM62P SoC, add the device-tree > nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi" > file. > > Co-developed-by: Ravi Gunasekaran <r-gunasekaran@xxxxxx> > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@xxxxxx> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx> Acked-by: Roger Quadros <rogerq@xxxxxxxxxx>
