On Tue, May 28, 2024 at 03:26:11PM +0300, Roger Quadros wrote:
[...]
> >
> > +#include <dt-bindings/phy/phy-cadence.h>
> > #include <dt-bindings/phy/phy-ti.h>
> >
> > /*
> > @@ -96,6 +97,35 @@ serdes1: serdes@f010000 {
> > };
> > };
> >
> > + pcie0_rc: pcie@f102000 {
>
> Please split PCIe node addition in to separate patch. hopefully you can squash it with patches that
> add USB, SERDES0 and SERDES1 to k3-j722s-main.dtsi.
I will do so in the v4 series. Thank you for reviewing and sharing your
feedback on this series.
Regards,
Siddharth.
