The variable naming in the various OEN functions has been confusing. We
were passing the _pin variable from rzg2l_pinctrl_pinconf_get() and
rzg2l_pinctrl_pinconf_set() as the offset argument to rzg2l_read_oen()
and rzg2l_write_oen(), when this is not a register offset.
What we actually need here is the port index, so that we can compare
this to oen_max_port.
We can also clean up rzg2l_pin_to_oen_bit(), removing an unnecessary
branch and clarifying the variable naming.
Signed-off-by: Paul Barker <paul.barker.ct@xxxxxxxxxxxxxx>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index c3256bfde502..724308cd5a37 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -1025,18 +1025,17 @@ static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
return true;
}
-static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
+static u8 rzg2l_pin_to_oen_bit(u32 port, u8 pin, u8 max_port)
{
- if (pin)
- pin *= 2;
+ u8 bit = pin * 2;
- if (offset / RZG2L_PINS_PER_PORT == max_port)
- pin += 1;
+ if (port == max_port)
+ bit += 1;
- return pin;
+ return bit;
}
-static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
+static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 port, u8 pin)
{
u8 max_port = pctrl->data->hwcfg->oen_max_port;
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
@@ -1045,12 +1044,12 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8
if (!rzg2l_oen_is_supported(caps, pin, max_pin))
return 0;
- bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
+ bit = rzg2l_pin_to_oen_bit(port, pin, max_port);
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
}
-static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
+static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 port, u8 pin, u8 oen)
{
u8 max_port = pctrl->data->hwcfg->oen_max_port;
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
@@ -1060,7 +1059,7 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8
if (!rzg2l_oen_is_supported(caps, pin, max_pin))
return -EINVAL;
- bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
+ bit = rzg2l_pin_to_oen_bit(port, pin, max_port);
spin_lock_irqsave(&pctrl->lock, flags);
val = readb(pctrl->base + ETH_MODE);
@@ -1112,7 +1111,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_OUTPUT_ENABLE:
- arg = rzg2l_read_oen(pctrl, cfg, _pin, bit);
+ arg = rzg2l_read_oen(pctrl, cfg, RZG2L_PIN_ID_TO_PORT(_pin), bit);
if (!arg)
return -EINVAL;
break;
@@ -1220,7 +1219,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_OUTPUT_ENABLE:
arg = pinconf_to_config_argument(_configs[i]);
- ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg);
+ ret = rzg2l_write_oen(pctrl, cfg,
+ RZG2L_PIN_ID_TO_PORT(_pin), bit, !!arg);
if (ret)
return ret;
break;
--
2.39.2
