Hello, On Sat, Apr 06, 2024 at 02:34:13PM +0800, Jingbao Qiu wrote: > Implement the PWM driver for CV1800. > > Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@xxxxxxxxx> > --- > drivers/pwm/Kconfig | 10 ++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-cv1800.c | 296 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 307 insertions(+) > create mode 100644 drivers/pwm/pwm-cv1800.c > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 1dd7921194f5..3869ca022aeb 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -182,6 +182,16 @@ config PWM_CROS_EC > PWM driver for exposing a PWM attached to the ChromeOS Embedded > Controller. > > +config PWM_CV1800 > + tristate "Sophgo CV1800 PWM driver" > + depends on ARCH_SOPHGO || COMPILE_TEST > + help > + Generic PWM framework driver for the Sophgo CV1800 series > + SoCs. > + > + To compile this driver as a module, build the dependecies > + as modules, this will be called pwm-cv1800. > + > config PWM_DWC_CORE > tristate > depends on HAS_IOMEM > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index 90913519f11a..6295e2259efc 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -14,6 +14,7 @@ obj-$(CONFIG_PWM_CLK) += pwm-clk.o > obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o > obj-$(CONFIG_PWM_CRC) += pwm-crc.o > obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o > +obj-$(CONFIG_PWM_CV1800) += pwm-cv1800.o > obj-$(CONFIG_PWM_DWC_CORE) += pwm-dwc-core.o > obj-$(CONFIG_PWM_DWC) += pwm-dwc.o > obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o > diff --git a/drivers/pwm/pwm-cv1800.c b/drivers/pwm/pwm-cv1800.c > new file mode 100644 > index 000000000000..37a6be3f63aa > --- /dev/null > +++ b/drivers/pwm/pwm-cv1800.c > @@ -0,0 +1,296 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Sophgo CV1800 PWM driver > + * Author: Jingbao Qiu <qiujingbao.dlmu@xxxxxxxxx> > + * > + * Limitations: > + * - It output low when PWM channel disabled. Just to be sure: the output is low independant of the POLARITY register? > + * - This pwm device supports dynamic loading of PWM parameters. When PWMSTART > + * is written from 0 to 1, the register value (HLPERIODn, PERIODn) will be > + * temporarily stored inside the PWM. If you want to dynamically change the > + * waveform during PWM output, after writing the new value to HLPERIODn and > + * PERIODn, write 1 and then 0 to PWMUPDATE[n] to make the new value effective. > + * - Supports up to Rate/2 output, and the lowest is about Rate/(2^30-1). > + * - By setting HLPERIODn to 0, can produce 100% duty cycle. > + * - This hardware could support inverted polarity. By default, the value of the > + * POLARITY register is 0x0. This means that HLPERIOD represents the number > + * of low level beats. > + * - This hardware supports input mode and output mode, implemented through the > + * Output-Enable/OE register. However, this driver has not yet implemented > + * capture callback. > + */ > + > +#include <linux/clk.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/pwm.h> > +#include <linux/regmap.h> > + > +#define PWM_CV1800_HLPERIOD_BASE 0x00 > +#define PWM_CV1800_PERIOD_BASE 0x04 > +#define PWM_CV1800_POLARITY 0x40 > +#define PWM_CV1800_START 0x44 > +#define PWM_CV1800_DONE 0x48 > +#define PWM_CV1800_UPDATE 0x4c > +#define PWM_CV1800_OE 0xd0 > + > +#define PWM_CV1800_HLPERIOD(n) (PWM_CV1800_HLPERIOD_BASE + ((n)*0x08)) > +#define PWM_CV1800_PERIOD(n) (PWM_CV1800_PERIOD_BASE + ((n)*0x08)) > + > +#define PWM_CV1800_UPDATE_MASK(n) (BIT(0) << (n)) > +#define PWM_CV1800_OE_MASK(n) (BIT(0) << (n)) > +#define PWM_CV1800_START_MASK(n) (BIT(0) << (n)) > +#define PWM_CV1800_POLARITY_MASK(n) (BIT(0) << (n)) > + > +#define PWM_CV1800_MAXPERIOD 0x3fffffff > +#define PWM_CV1800_MINPERIOD 2 > +#define PWM_CV1800_CHANNELS 4 > +#define PWM_CV1800_PERIOD_RESET BIT(1) > +#define PWM_CV1800_HLPERIOD_RESET BIT(0) > +#define PWM_CV1800_REG_DISABLE 0x00U > +#define PWM_CV1800_REG_ENABLE(n) (BIT(0) << (n)) BIT(n)? > + > +struct cv1800_pwm { > + struct regmap *map; > + struct clk *clk; > + unsigned long clk_rate; > +}; > + > +static inline struct cv1800_pwm *to_cv1800_pwm_dev(struct pwm_chip *chip) > +{ > + return pwmchip_get_drvdata(chip); > +} > + > +static const struct regmap_config cv1800_pwm_regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > +}; > + > +static int cv1800_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, > + bool enable) > +{ > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > + u32 pwm_enable, state; > + > + regmap_read(priv->map, PWM_CV1800_START, &pwm_enable); > + pwm_enable &= PWM_CV1800_START_MASK(pwm->hwpwm); > + > + /* > + * If the parameters are changed during runtime, Register needs > + * to be updated to take effect. > + */ > + if (pwm_enable && enable) { > + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, > + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, > + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), > + PWM_CV1800_REG_DISABLE); I think using a plain 0 instead of PWM_CV1800_REG_DISABLE would be a tad clearer. > + } else if (!pwm_enable && enable) { > + regmap_update_bits(priv->map, PWM_CV1800_START, > + PWM_CV1800_START_MASK(pwm->hwpwm), > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > + } else if (pwm_enable && !enable) { > + regmap_update_bits(priv->map, PWM_CV1800_START, > + PWM_CV1800_START_MASK(pwm->hwpwm), > + PWM_CV1800_REG_DISABLE); > + } > + > + /* check and set OE/Output-Enable mode */ > + regmap_read(priv->map, PWM_CV1800_OE, &state); > + state &= PWM_CV1800_OE_MASK(pwm->hwpwm); > + > + if (state == PWM_CV1800_REG_DISABLE && enable) Here I'd use: regmap_read(priv->map, PWM_CV1800_OE, &state); if ((state & BIT(pwm->hwpwm)) && enable) > + regmap_update_bits(priv->map, PWM_CV1800_OE, > + PWM_CV1800_OE_MASK(pwm->hwpwm), > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > + > + return 0; > +} > + > [...] > +static int cv1800_pwm_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct cv1800_pwm *priv; > + struct pwm_chip *chip; > + void __iomem *base; > + int ret; > + > + chip = devm_pwmchip_alloc(dev, PWM_CV1800_CHANNELS, sizeof(*priv)); > + if (!chip) > + return PTR_ERR(chip); > + priv = to_cv1800_pwm_dev(chip); > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + priv->map = devm_regmap_init_mmio(&pdev->dev, base, > + &cv1800_pwm_regmap_config); > + if (IS_ERR(priv->map)) > + return PTR_ERR(priv->map); devm_regmap_init_mmio() doesnt' emit an error message on failure, so please add one here. > + priv->clk = devm_clk_get_enabled(&pdev->dev, NULL); > + if (IS_ERR(priv->clk)) > + return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), > + "clk not found\n"); > + Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ |
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