There are four PCIe ports on IPQ9574, pcie0 thru pcie3. This series
addresses pcie2, which is a gen3x2 port. The board I have only uses
pcie2, and that's the only one enabled in this series.
I believe this makes sense as a monolithic series, as the individual
pieces are not that useful by themselves.
In v2, I've had some issues regarding the dt schema checks. For
transparency, I used the following test invocations to test v3:
make dt_binding_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml
make dtbs_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml
Changes since v2:
- reworked resets in qcom,pcie.yaml to resolve dt schema errors
- constrained "reg" in qcom,pcie.yaml
- reworked min/max intems in qcom,ipq8074-qmp-pcie-phy.yaml
- dropped msi-parent for pcie node, as it is handled by "msi" IRQ
Changes since v1:
- updated new tables in phy-qcom-qmp-pcie.c to use lowercase hex numbers
- reorganized qcom,ipq8074-qmp-pcie-phy.yaml to use a single list of clocks
- reorganized qcom,pcie.yaml to include clocks+resets per compatible
- Renamed "pcie2_qmp_phy" label to "pcie2_phy"
- moved "ranges" property of pcie@20000000 higher up
Alexandru Gagniuc (7):
dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574
clk: qcom: gcc-ipq9574: Add PCIe pipe clocks
dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller
PCI: qcom: Add support for IPQ9574
dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY
phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY
arm64: dts: qcom: ipq9574: add PCIe2 nodes
.../devicetree/bindings/pci/qcom,pcie.yaml | 35 +++++
.../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 36 ++++-
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 93 +++++++++++-
drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++
drivers/pci/controller/dwc/pcie-qcom.c | 13 +-
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++-
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 +
8 files changed, 400 insertions(+), 7 deletions(-)
--
2.40.1
