On Tue, Apr 02, 2024 at 10:23:45AM -0400, Frank Li wrote: > On Tue, Apr 02, 2024 at 01:45:03PM +0800, Richard Zhu wrote: > > Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. > > - Use the controller ID to specify which controller is binded to the > > PHY. > > - Introduce one HSIO configuration, mandatory required to set > > "PCIE_AB_SELECT" and "PHY_X1_EPCS_SEL" during the initialization. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx> > > You missed all conor's comments. > Please double check v1's comments. > > + fsl,refclk-pad-mode: > > + description: | > > + Specifies the mode of the refclk pad used. It can be UNUSED(PHY > > + refclock is derived from SoC internal source), INPUT(PHY refclock > > + is provided externally via the refclk pad) or OUTPUT(PHY refclock > > + is derived from SoC internal source and provided on the refclk pad). > > + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants > > + to be used. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + enum: [ 0, 1, 2 ] > > I remember needn't enum because there are header file. Yah, specifically my comments about this property were missed and were probably the most meaningful comments I left. Thanks for the reminder Frank.
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