Hi Conor, > -----Original Message----- > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > Sent: Wednesday, March 20, 2024 4:09 PM > To: Conor Dooley <conor@xxxxxxxxxx> > Cc: Joshua Yeong <joshua.yeong@xxxxxxxxxxxxxxxx>; > paul.walmsley@xxxxxxxxxx; palmer@xxxxxxxxxxx; aou@xxxxxxxxxxxxxxxxx; > geert+renesas@xxxxxxxxx; prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx; > alexghiti@xxxxxxxxxxxx; evan@xxxxxxxxxxxx; ajones@xxxxxxxxxxxxxxxx; > heiko@xxxxxxxxx; guoren@xxxxxxxxxx; uwu@xxxxxxxxxx; > jszhang@xxxxxxxxxx; robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; > conor+dt@xxxxxxxxxx; Leyfoon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx>; JeeHeng > Sia <jeeheng.sia@xxxxxxxxxxxxxxxx>; linux-riscv@xxxxxxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx > Subject: Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller > > On Sun, Mar 17, 2024 at 03:01:05PM +0000, Conor Dooley wrote: > > On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote: > > > StarFive's StarLink-500 Cache Controller flush/invalidates cache > > > using non- conventional CMO method. This driver provides the cache > > > handling on StarFive RISC-V SoC. > > > > Unlike the other "non-conventional" CMO methods, the jh8100 does not > > pre-date the Zicbom extension. Why has that not been implemented? > > Stefan pointed out on IRC yesterday that one of the main selling points is the > ease of operating on large ranges. > > > How many peripherals on the jh8100 rely on non-coherent DMA? JH8100 integrates in-house matured/stable CPU but it is a bit dated today. However, our newer generation of CPU should already support this extension. Most of the peripherals are coherent except mainly multimedia peripheral. Regards, Joshua > > > > Cheers, > > Conor. >
