From: Chen Wang <unicorn_wang@xxxxxxxxxxx> Add bindings for the clocks of which configuration registers are in the range of SYS_CTRL in the memory-map. Signed-off-by: Chen Wang <unicorn_wang@xxxxxxxxxxx> . --- .../bindings/clock/sophgo,sg2042-sysclk.yaml | 44 +++++++++++++ .../dt-bindings/clock/sophgo,sg2042-sysclk.h | 63 +++++++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-sysclk.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-sysclk.h diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-sysclk.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-sysclk.yaml new file mode 100644 index 000000000000..93b0631dcd0d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-sysclk.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-sysclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Clock Generator in System-Control + +description: + These clocks have configuration registers in the SYS_CTRL range of memory-map. + So the node should be a child of system-control node. + +maintainers: + - Chen Wang <unicorn_wang@xxxxxxxxxxx> + +properties: + compatible: + const: sophgo,sg2042-sysclk + + clocks: + items: + - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-sysclk.h> for valid indices. + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "sophgo,sg2042-sysclk"; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/sophgo,sg2042-sysclk.h b/include/dt-bindings/clock/sophgo,sg2042-sysclk.h new file mode 100644 index 000000000000..f7a9fbce16f8 --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2042-sysclk.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2042_SYSCLK_H__ +#define __DT_BINDINGS_SOPHGO_SG2042_SYSCLK_H__ + +#define MPLL_CLK 0 +#define FPLL_CLK 1 +#define DPLL0_CLK 2 +#define DPLL1_CLK 3 + +#define GATE_CLK_RXU0 4 +#define GATE_CLK_RXU1 5 +#define GATE_CLK_RXU2 6 +#define GATE_CLK_RXU3 7 +#define GATE_CLK_RXU4 8 +#define GATE_CLK_RXU5 9 +#define GATE_CLK_RXU6 10 +#define GATE_CLK_RXU7 11 +#define GATE_CLK_RXU8 12 +#define GATE_CLK_RXU9 13 +#define GATE_CLK_RXU10 14 +#define GATE_CLK_RXU11 15 +#define GATE_CLK_RXU12 16 +#define GATE_CLK_RXU13 17 +#define GATE_CLK_RXU14 18 +#define GATE_CLK_RXU15 19 +#define GATE_CLK_RXU16 20 +#define GATE_CLK_RXU17 21 +#define GATE_CLK_RXU18 22 +#define GATE_CLK_RXU19 23 +#define GATE_CLK_RXU20 24 +#define GATE_CLK_RXU21 25 +#define GATE_CLK_RXU22 26 +#define GATE_CLK_RXU23 27 +#define GATE_CLK_RXU24 28 +#define GATE_CLK_RXU25 29 +#define GATE_CLK_RXU26 30 +#define GATE_CLK_RXU27 31 +#define GATE_CLK_RXU28 32 +#define GATE_CLK_RXU29 33 +#define GATE_CLK_RXU30 34 +#define GATE_CLK_RXU31 35 +#define GATE_CLK_MP0 36 +#define GATE_CLK_MP1 37 +#define GATE_CLK_MP2 38 +#define GATE_CLK_MP3 39 +#define GATE_CLK_MP4 40 +#define GATE_CLK_MP5 41 +#define GATE_CLK_MP6 42 +#define GATE_CLK_MP7 43 +#define GATE_CLK_MP8 44 +#define GATE_CLK_MP9 45 +#define GATE_CLK_MP10 46 +#define GATE_CLK_MP11 47 +#define GATE_CLK_MP12 48 +#define GATE_CLK_MP13 49 +#define GATE_CLK_MP14 50 +#define GATE_CLK_MP15 51 + +#endif /* __DT_BINDINGS_SOPHGO_SG2042_SYSCLK_H__ */ -- 2.25.1
