On 14-12-2023 17:47, Nishanth Menon wrote: ... >> >> Yes, you are right! Edge-Triggered interrupts shouldn't be shared. I missed >> noticing this. Thank you for pointing it out. Since the SoC only supports >> Edge-Triggered interrupts, I believe that the correct decision would be to use >> the interrupt for only one of the two PHYs, while leaving the other PHY in >> polled mode of operation which is the default. >> >> Kindly let me know if this is acceptable and I shall update this patch accordingly. > > Sounds like a bug in board design there (due to an choice of IP > limitation) - I suggest getting it noted in board documentation and > refer to the errata in the second phy (else folks will wonder why we > aren't using interrupts on the second phy. Thank you for your suggestion on the next steps to be taken. I will ensure that the board documentation is updated. Additionally, in the v3 patch I will add a comment within the "icssg2_phy0" node indicating that the interrupt mode of operation is only being enabled for "icssg2_phy0" due to the interrupt being an edge-triggered interrupt which cannot be shared among both the PHYs. And for that reason "icssg2_phy1" is being left in the default polled mode of operation. -- Regards, Siddharth.
