On 11/15/23 2:22 PM, Siddharth Vadapalli wrote: > Add overlay to enable the PCIE0 instance of PCIe on J721E-EVM in > Endpoint mode of operation. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx> > --- > arch/arm64/boot/dts/ti/Makefile | 3 ++ > .../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 53 +++++++++++++++++++ > 2 files changed, 56 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso > > diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile > index 77a347f9f47d..5620db44d4dc 100644 > --- a/arch/arm64/boot/dts/ti/Makefile > +++ b/arch/arm64/boot/dts/ti/Makefile > @@ -66,6 +66,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb > k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo > dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb > dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb > +k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-evm.dtb k3-j721e-evm-pcie0-ep.dtbo > +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtb > dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo > dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb > > @@ -85,4 +87,5 @@ DTC_FLAGS_k3-am625-sk += -@ > DTC_FLAGS_k3-am62-lp-sk += -@ > DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ > DTC_FLAGS_k3-j721e-common-proc-board += -@ > +DTC_FLAGS_k3-j721e-evm += -@ > DTC_FLAGS_k3-j721s2-common-proc-board += -@ > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso > new file mode 100644 > index 000000000000..0c82a13b65a4 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso > @@ -0,0 +1,53 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/** > + * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the > + * J7 common processor board. > + * > + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM > + * > + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +/dts-v1/; > +/plugin/; > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/soc/ti,sci_pm_domain.h> > + > +#include "k3-pinctrl.h" > + > +/* > + * Since Root Complex and Endpoint modes are mutually exclusive > + * disable Root Complex mode. > + */ > +&pcie0_rc { > + status = "disabled"; > +}; > + > +&cbass_main { > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic500>; > + > + pcie0_ep: pcie-ep@2900000 { > + compatible = "ti,j721e-pcie-ep"; > + reg = <0x00 0x02900000 0x00 0x1000>, > + <0x00 0x02907000 0x00 0x400>, > + <0x00 0x0d000000 0x00 0x00800000>, > + <0x00 0x10000000 0x00 0x08000000>; > + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; > + interrupt-names = "link_state"; > + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; > + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; > + max-link-speed = <3>; > + num-lanes = <1>; > + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 239 1>; > + clock-names = "fck"; > + max-functions = /bits/ 8 <6>; > + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; > + dma-coherent; > + phys = <&serdes0_pcie_link>; > + phy-names = "pcie-phy"; > + }; > +}; Reviewed-by: Ravi Gunasekaran <r-gunasekaran@xxxxxx> -- Regards, Ravi
