On Thu, Nov 09, 2023 at 09:51:47PM +0000, Daniel Golle wrote:
> MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
> it in order to configure and monitor the Ethernet SerDes link in
> USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
> legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
> interface modes are also available.
I think this binding is based on the implementation than on hardware.
What I believe you have is this setup:
.---- LynxI PCS ----.
MAC ---+ +--- PEXTP --- world
`--- USXGMII PCS ---'
You are representing the PEXTP as a separate entity in DT, but then
you're representing the LynxI PCS and the USXGMII PCS as a single
block, which seems to be how you've decided to implement it.
Given that the LynxI PCS is already in use elsewhere in the Mediatek
range, I suggest that the LynxI PCS is one block of IP, and the USXGMII
PCS is a separate block of IP.
1) Would it not be better to model the two PCS seperately?
2) The addition of the SGMII reset needs more information - is this
controlling a reset for the LynxI block? If so, it should be part
of a LynxI PCS binding.
3) The PEXTP is presumably a separate block which can be shared between
several devices - for example, the LynxI, USXGMII, and probably SATA
and PCIe as well. From the 802.3's network model, the PEXTP is the
PMA/PMD.
From the point of view of 802.3's model, a network interface has
various layers such as the MAC, PCS and PMA/PMD, and sitting above
these layers is the management of the system. Rather than chasing
the data flow (which in a network device can be complex) wouldn't
it be better to continue with the 802.3 model as we are doing with
other devices, rather than trying to go with a new approach here?
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
