On Thu, Nov 09, 2023 at 09:51:47PM +0000, Daniel Golle wrote: > MediaTek's USXGMII can be found in the MT7988 SoC. We need to access > it in order to configure and monitor the Ethernet SerDes link in > USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped > legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those > interface modes are also available. > > Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx> > --- > .../bindings/net/pcs/mediatek,usxgmii.yaml | 105 ++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml > > diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml > new file mode 100644 > index 0000000000000..199cf47859e31 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek USXGMII PCS > + > +maintainers: > + - Daniel Golle <daniel@xxxxxxxxxxxxxx> > + > +description: > + The MediaTek USXGMII PCS provides physical link control and status > + for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces > + provided by the PEXTP PHY. > + In order to also support legacy 2500Base-X, 1000Base-X and Cisco > + SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to > + provide those interfaces modes on the same SerDes interfaces shared > + with the USXGMII PCS. > + > +properties: > + $nodename: > + pattern: "^pcs@[0-9a-f]+$" > + > + compatible: > + const: mediatek,mt7988-usxgmiisys > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: USXGMII top-level clock > + - description: SGMII top-level clock > + - description: SGMII subsystem TX clock > + - description: SGMII subsystem RX clock > + - description: XFI PLL clock > + > + clock-names: > + items: > + - const: usxgmii > + - const: sgmii_sel > + - const: sgmii_tx > + - const: sgmii_rx > + - const: xfi_pll > + > + phys: > + items: > + - description: PEXTP SerDes PHY > + > + mediatek,sgmiisys: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon node of the corresponding SGMII LynxI PCS. > + > + resets: > + items: > + - description: XFI reset > + - description: SGMII reset > + > + reset-names: > + items: > + - const: xfi > + - const: sgmii > + > + "#pcs-cells": There is no such property defined. Rob
