From: Chen Wang <unicorn_wang@xxxxxxxxxxx> Add bindings for the clock generator on the SG2042 RISC-V SoC. Signed-off-by: Chen Wang <unicorn_wang@xxxxxxxxxxx> --- .../clock/sophgo/sophgo,sg2042-clkgen.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml diff --git a/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml new file mode 100644 index 000000000000..e372d5dca5b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Clock Generator + +maintainers: + - Chen Wang <unicorn_wang@xxxxxxxxxxx> + +properties: + compatible: + const: sophgo,sg2042-clkgen + + system-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller syscon node. + description: + The phandle to System Register Controller syscon node. + + clocks: + items: + - description: Clock Generation IC (25 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo-sg2042-clk.h> for valid indices. + +required: + - compatible + - system-ctrl + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "sophgo,sg2042-clkgen"; + clocks = <&cgi>; + system-ctrl = <&sys_ctrl>; + #clock-cells = <1>; + }; -- 2.25.1
