Add the reset device tree node to cv1800b SoC reusing the
pinctrl-single driver.
Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
---
arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
2 files changed, 29 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h
diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
new file mode 100644
index 000000000000..ed78b6fb3142
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
+ *
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@xxxxxxxxxx>
+ */
+#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
+#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
+
+#define MUX_M0 0
+#define MUX_M1 1
+#define MUX_M2 2
+#define MUX_M3 3
+#define MUX_M4 4
+#define MUX_M5 5
+#define MUX_M6 6
+#define MUX_M7 7
+
+#endif
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index e04df04a91c0..7a44d8e8672b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -6,6 +6,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sophgo,cv1800b-reset.h>
+#include "cv-pinctrl.h"
+
/ {
compatible = "sophgo,cv1800b";
#address-cells = <1>;
@@ -55,6 +57,14 @@ soc {
dma-noncoherent;
ranges;
+ pinctrl0: pinctrl@3001000 {
+ compatible = "pinctrl-single";
+ reg = <0x3001000 0x130>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000007>;
+ };
+
rst: reset-controller@3003000 {
compatible = "sophgo,cv1800b-reset";
reg = <0x03003000 0x1000>;
--
2.42.0
