This series adds support for the StarFive JH7100 SoC to the SiFive cache controller driver. The JH7100 was a "development version" of the JH7110 used on the BeagleV Starlight and VisionFive V1 boards. It has non-coherent peripheral DMAs but was designed before the standard RISC-V Zicbom extension, so it neeeds support in this driver for non-standard cache management. Since v1: - Fix email threading, hopefully. - Drop sifive,ccache-ops device tree property and just match on the compatible. (Conor) Emil Renner Berthing (2): dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible soc: sifive: ccache: Add StarFive JH7100 support .../bindings/cache/sifive,ccache0.yaml | 6 +- drivers/soc/sifive/sifive_ccache.c | 62 ++++++++++++++++++- 2 files changed, 65 insertions(+), 3 deletions(-) -- 2.40.1
