Re: [PATCH 1/2] dt-bindings: w1: Add YAML DT Schema for AMD w1 master and MAINTAINERS entry

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On 13/10/2023 18:18, Rob Herring wrote:
i_1wire_master. It is a soft HDL core.
Only 1 version of it (ever)? Like other PL IP, it needs a version number
(and not v1, v2, etc. made up by you). Really, your versioning scheme
should be documented (like
bindings/sifive/sifive-blocks-ip-versioning.txt), but Xilinx started
versioning stuff some time back.

I've specified the PL IP to have both an ID and version number register in it, which is queried by the driver on probe.  As such we can version autodiscover.  Should there be incompatibilty in the driver due to new features in future PL IP, the major version number in the register will increment and the same driver can be extended to support the modified behaviour.  The default code in this first version will check to ensure major is at 1. I'm working with our IP group to encourage that all new IP have this mechanism moving forwards, as registers are a lot cheaper in logic than they used to be.

+  if (ver_major != 1) {
+     dev_err(dev, "AMD AXI W1 Master version %u.%u is not supported by this driver",
+        ver_major, ver_minor);
+     return -ENODEV;
+  }

Also, 'master' is not considered great terminology nowadays. Perhaps the
catalog name should be updated.

Agreed -  I've used the term to fit with others in the subsystem.  Would this be something that is changed and aligned across W1?  If so I'm happy to get the HDL IP renamed and binding / driver documentation to match if an alternative designator to replace master has already been chosen and standardised across 1Wire.

Regards
Kris





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