On Fri, Oct 13, 2023 at 04:23:15PM +0100, Kris Chaplin wrote: > > On 13/10/2023 16:07, Conor Dooley wrote: > > On Fri, Oct 13, 2023 at 05:04:32PM +0200, Krzysztof Kozlowski wrote: > > > > > > That's a quite generic compatible. axi is ARM term, 1-wire is the name > > > of the bus and master is the role. Concatenating three common words does > > > not create unique device name. Compatibles are supposed to be specific > > > and this is really relaxed. Anything can be over AXI, everything in > > > 1wire is 1wire and every master device is a master. > > Given the vendor (and the title of the binding) this is almost certainly > > an FPGA IP core, so the generic name is understandable. Using the exact > > name of the IP in the AMD/Xilinx catalog probably is the best choice? > > Indeed this is an Programmable Logic IP core - the official name of the core > in our catalog is axi_1wire_master. It is a soft HDL core. Only 1 version of it (ever)? Like other PL IP, it needs a version number (and not v1, v2, etc. made up by you). Really, your versioning scheme should be documented (like bindings/sifive/sifive-blocks-ip-versioning.txt), but Xilinx started versioning stuff some time back. Also, 'master' is not considered great terminology nowadays. Perhaps the catalog name should be updated. Rob
