在2023年10月4日十月 下午5:10，Gregory CLEMENT写道：
> From: Vladimir Kondratiev <vladimir.kondratiev@xxxxxxxxx>
>
> Support platforms where RAM is mapped beyond 32-bit.
>
> The kernel parameter ddr32_alias allows to setup the alias to point
> outside the first 4 GB of memory.
Are you trying to fix the problem that if kernel text is loaded in
XKPHYS there is no way to to set EBASE to that region?
The common practice for other 64bit MIPS system is to load kernel
in KSEG0 and add low 4G mirror with rest of the high memory to buddy
system. By doing this Kernel still have access to all memory beyond
32 bit, the only draw back is Kernel's text and data can't be relocted
beyond 32-bit.
Loading kernel into KSEG0 (i.e. with KBUILD_SYM32) have significant benefit
on performance, so I think you shouldn't try to load kernel into XKPHYS
without a good reason, but it might be helpful to add a BUG_ON at
CPS driver to handle such situation.
Btw: Is your target hardware publicly available? Folks at CIP United
are looking for EyeQ5 boards for a while, they are supporting MIPS R6
support at various projects.
Thanks
Jiaxun
>
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@xxxxxxxxx>
> Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
> ---
> arch/mips/kernel/smp-cps.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index 47e76722a306..fcfb19487612 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -34,6 +34,16 @@ static unsigned __init core_vpe_count(unsigned int
> cluster, unsigned core)
> return min(smp_max_threads, mips_cps_numvps(cluster, core));
> }
>
> +static int ddr32_alias;
> +
> +static int __init ddr32_alias_setup(char *str)
> +{
> + get_option(&str, &ddr32_alias);
> +
> + return 0;
> +}
> +early_param("ddr32_alias", ddr32_alias_setup);
> +
> /**
> * plat_core_entry - query reset vector for NMI/reset
> *
> @@ -52,7 +62,7 @@ static u32 plat_core_entry(void)
> {
> #if defined(CONFIG_USE_XKPHYS)
> return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff)
> - | CM_GCR_Cx_RESET_BASE_MODE;
> + | ddr32_alias | CM_GCR_Cx_RESET_BASE_MODE;
> #else
> return CKSEG1ADDR((unsigned long)mips_cps_core_entry);
> #endif
> --
> 2.40.1
--
- Jiaxun
