On 25/09/2023 09:46, Jayesh Choudhary wrote:
Hello Maxime,
On 17/08/23 16:24, Maxime Ripard wrote:
Hi,
On Thu, Aug 03, 2023 at 01:34:39PM +0530, Jayesh Choudhary wrote:
From: Rahul T R <r-ravikumar@xxxxxx>
Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
same as DSS IP in J721E, so same compatible is being used.
The DP is Cadence MHDP8546.
[...]
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
As far as I can see, this compatible limits the (DPI) pixel clock to
160MHz, but the TRM seems to mention that it's 600MHz?
Is it expected?
I am unsure about why the max DPI pixel clock was set to 170MHz for
videoport bus type DISPC_VP_DPI.
Bus type DISPC_VP_DPI is used only for tfp410 bridge which can support
min 6.06ns pixel period (165MHz pixel clk).
I think the max value however should still be independent to what the
bridge can support.
We can look into this issue independent to this series.
Tomi,
Any comments here..
There should not be any issue making the max pixel clock for DPI bus
type 600 MHz as well????
The dispc can output at high frequency, but when it goes to DPI, meaning
a parallel video bus outside the SoC, we move into another domain. And
even if the signals would be ok at the SoC's pins at higher freqs, I'm
sure they would degrade quickly with a cable going to the panel
(Disclaimer: I'm no HW engineer =)). If I had to guess, I'd guess that
200 MHz would still be fine-ish in most cases, but I have hard time
believing that a 300 MHz DPI signal would look valid in an oscilloscope.
With a quick look, the J7 datasheet says "Cycle time, VOUT(x)_PCLK " has
min 6.06 ns. As that's the same as the one you mention for tfp410, and
results in 165MHz, it sounds to me that it's just a safe limit, not any
kind of real limit.
On DRA76, I think the "offical" DPI max was the same, but running with
~210 MHz still worked fine, for the particular pieces of hardware I had.
So... I'd keep it (at least near) the official limit, unless someone has
use cases which require higher frequencies.
Tomi
