Hello Maxime,
On 17/08/23 16:24, Maxime Ripard wrote:
Hi,
On Thu, Aug 03, 2023 at 01:34:39PM +0530, Jayesh Choudhary wrote:
From: Rahul T R <r-ravikumar@xxxxxx>
Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
same as DSS IP in J721E, so same compatible is being used.
The DP is Cadence MHDP8546.
[...]
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
As far as I can see, this compatible limits the (DPI) pixel clock to
160MHz, but the TRM seems to mention that it's 600MHz?
Is it expected?
I am unsure about why the max DPI pixel clock was set to 170MHz for
videoport bus type DISPC_VP_DPI.
Bus type DISPC_VP_DPI is used only for tfp410 bridge which can support
min 6.06ns pixel period (165MHz pixel clk).
I think the max value however should still be independent to what the
bridge can support.
We can look into this issue independent to this series.
Tomi,
Any comments here..
There should not be any issue making the max pixel clock for DPI bus
type 600 MHz as well????
-Jayesh
