Hi,
On Thu, Aug 03, 2023 at 01:34:39PM +0530, Jayesh Choudhary wrote:
> From: Rahul T R <r-ravikumar@xxxxxx>
>
> Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
> same as DSS IP in J721E, so same compatible is being used.
> The DP is Cadence MHDP8546.
>
> Signed-off-by: Rahul T R <r-ravikumar@xxxxxx>
> [j-choudhary@xxxxxx: move dss & mhdp node together in main, fix dss node]
> Signed-off-by: Jayesh Choudhary <j-choudhary@xxxxxx>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 63 ++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 446d7efa715f..824312b9ef9f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -1741,4 +1741,67 @@ c71_3: dsp@67800000 {
> resets = <&k3_reset 40 1>;
> firmware-name = "j784s4-c71_3-fw";
> };
> +
> + mhdp: bridge@a000000 {
> + compatible = "ti,j721e-mhdp8546";
> + reg = <0x0 0xa000000 0x0 0x30a00>,
> + <0x0 0x4f40000 0x0 0x20>;
> + reg-names = "mhdptx", "j721e-intg";
> + clocks = <&k3_clks 217 11>;
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
> + status = "disabled";
> +
> + dp0_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + dss: dss@4a00000 {
> + compatible = "ti,j721e-dss";
As far as I can see, this compatible limits the (DPI) pixel clock to
160MHz, but the TRM seems to mention that it's 600MHz?
Is it expected?
Maxime
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