This patchset is a third one in the series created in the framework of my Synopsys DW uMCTL2 DDRC-related work: [1: In-progress v4] EDAC/mc/synopsys: Various fixes and cleanups Link: https://lore.kernel.org/linux-edac/20230920191059.28395-1-fancer.lancer@xxxxxxxxx [2: In-progress v4] EDAC/synopsys: Add generic DDRC info and address mapping Link: https://lore.kernel.org/linux-edac/20230920192806.29960-1-fancer.lancer@xxxxxxxxx [3: In-progress v4] EDAC/synopsys: Add generic resources and Scrub support Link: ---you are looking at it--- Note the patchsets above must be merged in the same order as they are placed in the list in order to prevent conflicts. Nothing prevents them from being reviewed synchronously though. Any tests are very welcome. Thanks in advance. This is a final patchset in the framework of my Synopsys DW uMCTL2 DDRC work, which completes the driver updates with the new functionality. The series starts from extending the Synopsys DW uMCTL2 DDRC DT-schema with the controller specific IRQs, clocks and resets properties. In addition the Baikal-T1 DDRC is added to the DT-bindings since it's based on the DW uMCTL2 DDRC v2.61a. After that the driver is finally altered to informing the MCI core with the detected SDRAM ranks and making sure the detected errors are reported to the corresponding rank. Then the DDRC capabilities are extended with optional Scrub functionality. It's indeed possible to have the DW uMCTL2 controller with no HW-accelerated Scrub support (no RMW engine). In that case the MCI core is supposed to perform the erroneous location ECC update by means of the platform-specific scrub method. Then the error-injection functionality is fixed a bit. First since the driver now has the Sys<->SDRAM address translation infrastructure it can be utilized to convert the supplied poisonous system address to the SDRAM one. Thus there is no longer need in preserving the address in the device private data. Second a DebuFS node-based command to disable the error-injection feature is added (no idea why it hasn't been done in the first place). Afterwards a series of the IRQ-related patches goes. First introduce the individual DDRC event IRQs support in accordance with what has been added to the DT-bindings and what the native DW uMCTL2 DDR controller actually provides. Then aside to the ECC CE/UE errors detection, the DFI/SDRAM CRC/Parity errors report is added. It specifically useful for the DDR4 memory which has dedicated ALARM_n signal, but can be still utilized in the framework of the older protocols if the device DFI-PHY calculates the HIF-interface signals parity. Third after adding the platform clock/resets request procedure introduce the HW-accelerated Scrubber support. Its performance can be tuned by means of the sdram_scrub_rate SysFS node and the Core clock rate. Note it is possible to one-time-run the Scrubber in the back-to-back mode so to perform a burst-like scan of the entire SDRAM memory. At the patchset closure he DW uMCTL2 DDRC kernel config is finally fixed to be available not only on the Xilinx, Intel and MXC platforms, but on anyone including the Baikal-T1 SoC which has the DW uMCTL2 DDRC v2.61a on board. Changelog v2: - Replace "snps,ddrc-3.80a" compatible string with "snps,dw-umctl2-ddrc" in the example. - Move unrelated changes in to the dedicated patches. (@Krzysztof) - Use the IRQ macros in the example. (@Krzysztof) - Add a new patch: [PATCH v2 01/15] dt-bindings: memory: snps: Replace opencoded numbers with macros (@Krzysztof) - Add a new patch: [PATCH v2 03/15] dt-bindings: memory: snps: Convert the schema to being generic (@Krzysztof) - Drop the PHY CSR region. (@Rob) - Move the Baikal-T1 DDRC bindings to the separate DT-schema. Changelog v3: - Create common DT-schema instead of using the generic device DT-bindings. (@Rob) - Drop the merged in patches: [PATCH v2 01/15] dt-bindings: memory: snps: Replace opencoded numbers with macros [PATCH v2 02/15] dt-bindings: memory: snps: Extend schema with IRQs/resets/clocks props (@Krzysztof) Changelog v4: - Explicitly set snps_ddrc_info.dq_width for Baikal-T1 DDRC for better maintainability. - Explicitly set sys_app_map.minsize to SZ_256M instead of using a helper macro DDR_MIN_SARSIZE for Baikal-T1 DDRC. - Use div_u64() instead of do_div(). - Use FIELD_MAX() instead of open-coding the bitwise shift to find the max field value. - Fix inject_data_error string printing "Rank" word where "Col" is supposed to be. - Rebase onto the kernel v6.6-rcX. Signed-off-by: Serge Semin <fancer.lancer@xxxxxxxxx> Cc: Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xxxxxxxxxx> Cc: Dinh Nguyen <dinguyen@xxxxxxxxxx> Cc: Arnd Bergmann <arnd@xxxxxxxx> Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> Cc: Rob Herring <robh@xxxxxxxxxx> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Cc: devicetree@xxxxxxxxxxxxxxx Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx Cc: linux-edac@xxxxxxxxxxxxxxx Cc: linux-kernel@xxxxxxxxxxxxxxx Serge Semin (13): dt-bindings: memory: snps: Convert the schema to being generic dt-bindings: memory: Add BT1 DDRC DT-schema EDAC/synopsys: Add multi-ranked memory support EDAC/synopsys: Add optional ECC Scrub support EDAC/synopsys: Drop ECC poison address from private data EDAC/synopsys: Add data poisoning disable support EDAC/synopsys: Split up ECC UE/CE IRQs handler EDAC/synopsys: Add individual named ECC IRQs support EDAC/synopsys: Add DFI alert_n IRQ support EDAC/synopsys: Add reference clocks support EDAC/synopsys: Add ECC Scrubber support EDAC/synopsys: Drop vendor-specific arch dependency EDAC/synopsys: Add BT1 DDRC support .../memory-controllers/baikal,bt1-ddrc.yaml | 91 ++ .../snps,dw-umctl2-common.yaml | 75 ++ .../snps,dw-umctl2-ddrc.yaml | 57 +- drivers/edac/Kconfig | 1 - drivers/edac/synopsys_edac.c | 950 ++++++++++++++---- 5 files changed, 933 insertions(+), 241 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml create mode 100644 Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-common.yaml -- 2.41.0
