On Wed, 13 Sep 2023 14:40:10 +0530, MD Danish Anwar wrote: > In order to support half-duplex operation at 10M and 100M link speeds, the > PHY collision detection signal (COL) should be routed to ICSSG > GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal > and apply the CSMA/CD algorithm applicable for half duplex operation. A DT > property, "ti,half-duplex-capable" is introduced for this purpose. If > board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can > be added to eth node of ICSSG, MII port to support half duplex operation at > that port. > > Reviewed-by: Roger Quadros <rogerq@xxxxxxxxxx> > Signed-off-by: MD Danish Anwar <danishanwar@xxxxxx> > --- > Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
