On 07/08/2023 07:51, Radhey Shyam Pandey wrote: > Xilinx 1G/2.5G Ethernet Subsystem provides 32-bit AXI4-Stream buses to > move transmit and receive Ethernet data to and from the subsystem. > > These buses are designed to be used with an AXI Direct Memory Access(DMA) > IP or AXI Multichannel Direct Memory Access (MCDMA) IP core, AXI4-Stream > Data FIFO, or any other custom logic in any supported device. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
