Hi Krzysztof,
On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
<krzysztof.kozlowski@xxxxxxxxxx> wrote:
>
> On 20/07/2023 15:51, Eric Lin wrote:
> > This add YAML DT binding documentation for SiFive Private L2
> > cache controller
> >
> > Signed-off-by: Eric Lin <eric.lin@xxxxxxxxxx>
> > Reviewed-by: Zong Li <zong.li@xxxxxxxxxx>
> > Reviewed-by: Nick Hu <nick.hu@xxxxxxxxxx>
>
>
> ...
>
> > +properties:
> > + compatible:
> > + items:
> > + - const: sifive,pl2cache1
>
> I still have doubts that it is not used in any SoC. This is what you
> said last time: "is not part of any SoC."
> If not part of any SoC, then where is it? Why are you adding it to the
> kernel?
>
Sorry for the late reply. I didn't describe it clearly last time.
Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
The pl2cache0 is used in unmatched board SoC. The pl2cache1 is
utilized in our internal FPGA platform for evaluation; it's our core
IP.
>
>
> > + - const: cache
> > +
> > + cache-block-size: true
> > + cache-level: true
> > + cache-sets: true
> > + cache-size: true
> > + cache-unified: true
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + next-level-cache: true
> > +
> > +required:
> > + - compatible
> > + - cache-block-size
> > + - cache-level
> > + - cache-sets
> > + - cache-size
> > + - cache-unified
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + cache-controller@10104000 {
> > + compatible = "sifive,pl2cache1","cache";
>
> Missing space.
OK, I'll fix it in the next version.
>
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <512>;
> > + cache-size = <262144>;
> > + cache-unified;
> > + reg = <0x10104000 0x4000>;
>
> reg is after compatible.
OK, I'll fix it in the next version.
Thanks for your review.
Best regards,
Eric Lin
>
> > + next-level-cache = <&L4>;
> > + };
>
> Best regards,
> Krzysztof
>
