On 20/07/2023 15:51, Eric Lin wrote:
> This add YAML DT binding documentation for SiFive Private L2
> cache controller
>
> Signed-off-by: Eric Lin <eric.lin@xxxxxxxxxx>
> Reviewed-by: Zong Li <zong.li@xxxxxxxxxx>
> Reviewed-by: Nick Hu <nick.hu@xxxxxxxxxx>
...
> +properties:
> + compatible:
> + items:
> + - const: sifive,pl2cache1
I still have doubts that it is not used in any SoC. This is what you
said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the
kernel?
> + - const: cache
> +
> + cache-block-size: true
> + cache-level: true
> + cache-sets: true
> + cache-size: true
> + cache-unified: true
> +
> + reg:
> + maxItems: 1
> +
> + next-level-cache: true
> +
> +required:
> + - compatible
> + - cache-block-size
> + - cache-level
> + - cache-sets
> + - cache-size
> + - cache-unified
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + cache-controller@10104000 {
> + compatible = "sifive,pl2cache1","cache";
Missing space.
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <512>;
> + cache-size = <262144>;
> + cache-unified;
> + reg = <0x10104000 0x4000>;
reg is after compatible.
> + next-level-cache = <&L4>;
> + };
Best regards,
Krzysztof
