This add YAML DT binding documentation for SiFive Private L2 cache controller Signed-off-by: Eric Lin <eric.lin@xxxxxxxxxx> Reviewed-by: Zong Li <zong.li@xxxxxxxxxx> Reviewed-by: Nick Hu <nick.hu@xxxxxxxxxx> --- .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file mode 100644 index 000000000000..ee8356c5eeee --- /dev/null +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Private L2 Cache Controller + +maintainers: + - Greentime Hu <greentime.hu@xxxxxxxxxx> + - Eric Lin <eric.lin@xxxxxxxxxx> + +description: + The SiFive Private L2 Cache Controller is per core and + communicates with both the upstream L1 caches and + downstream L3 cache or memory, enabling a high-performance + cache subsystem. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +properties: + compatible: + items: + - const: sifive,pl2cache1 + - const: cache + + cache-block-size: true + cache-level: true + cache-sets: true + cache-size: true + cache-unified: true + + reg: + maxItems: 1 + + next-level-cache: true + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - reg + +additionalProperties: false + +examples: + - | + cache-controller@10104000 { + compatible = "sifive,pl2cache1","cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + reg = <0x10104000 0x4000>; + next-level-cache = <&L4>; + }; -- 2.40.1
