On 18:50-20230721, Jayesh Choudhary wrote: > From: Siddharth Vadapalli <s-vadapalli@xxxxxx> > > The system controller node manages the CTRL_MMR0 region. > Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx> > [j-choudhary@xxxxxx: Fix serdes_ln_ctrl node] > Signed-off-by: Jayesh Choudhary <j-choudhary@xxxxxx> > --- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index 11f163e5cadf..5a4da4eb8d3d 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -5,6 +5,10 @@ > * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ > */ > > +#include <dt-bindings/mux/mux.h> > + > +#include "k3-serdes.h" > + > &cbass_main { > msmc_ram: sram@70000000 { > compatible = "mmio-sram"; > @@ -26,6 +30,42 @@ l3cache-sram@200000 { > }; > }; > > + scm_conf: syscon@100000 { > + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; Would'nt a simple-bus work? https://lore.kernel.org/all/20230605205220.rjmcsi5tjn4auqa7@arose/ > + reg = <0x00 0x00100000 0x00 0x1c000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00 0x00 0x00100000 0x1c000>; > + > + serdes_ln_ctrl: mux-controller@4080 { > + compatible = "mmio-mux"; > + reg = <0x00004080 0x30>; > + #mux-control-cells = <1>; > + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ > + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ > + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ > + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ > + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ > + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ > + idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, > + <J784S4_SERDES0_LANE1_PCIE1_LANE1>, > + <J784S4_SERDES0_LANE2_IP3_UNUSED>, > + <J784S4_SERDES0_LANE3_USB>, > + <J784S4_SERDES1_LANE0_PCIE0_LANE0>, > + <J784S4_SERDES1_LANE1_PCIE0_LANE1>, > + <J784S4_SERDES1_LANE2_PCIE0_LANE2>, > + <J784S4_SERDES1_LANE3_PCIE0_LANE3>, > + <J784S4_SERDES2_LANE0_IP2_UNUSED>, > + <J784S4_SERDES2_LANE1_IP2_UNUSED>, > + <J784S4_SERDES2_LANE2_QSGMII_LANE1>, > + <J784S4_SERDES2_LANE3_QSGMII_LANE2>, > + <J784S4_SERDES4_LANE0_EDP_LANE0>, > + <J784S4_SERDES4_LANE1_EDP_LANE1>, > + <J784S4_SERDES4_LANE2_EDP_LANE2>, > + <J784S4_SERDES4_LANE3_EDP_LANE3>; > + }; > + }; > + > gic500: interrupt-controller@1800000 { > compatible = "arm,gic-v3"; > #address-cells = <2>; > -- > 2.25.1 > -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
