Add binding documentation for the Marvell GTI system watchdog driver. Signed-off-by: Bharat Bhushan <bbhushan2@xxxxxxxxxxx> --- v7: - Corrected compatible to have soc name - Converted marvell,wdt-timer-index to optional .../watchdog/marvell,octeontx2-wdt.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/marvell,octeontx2-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/marvell,octeontx2-wdt.yaml b/Documentation/devicetree/bindings/watchdog/marvell,octeontx2-wdt.yaml new file mode 100644 index 000000000000..72951b10f1f3 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/marvell,octeontx2-wdt.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/marvell,octeontx2-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Global Timer (GTI) system watchdog + +allOf: + - $ref: watchdog.yaml# + +maintainers: + - Bharat Bhushan <bbhushan2@xxxxxxxxxxx> + +properties: + compatible: + oneOf: + - const: marvell,octeontx2-wdt + - items: + - enum: + - marvell,octeontx2-95xx-wdt + - marvell,octeontx2-96xx-wdt + - marvell,octeontx2-98xx-wdt + - const: marvell,octeontx2-wdt + - const: marvell,cn10k-wdt + - items: + - enum: + - marvell,cn10kx-wdt + - marvell,cnf10kx-wdt + - const: marvell,cn10k-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + + clock-names: + minItems: 1 + + marvell,wdt-timer-index: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + description: + An SoC have many timers (up to 64), firmware can reserve one or more timer + for some other use case and configures one of the global timer as watchdog + timer. Firmware will update this field with the timer number configured + as watchdog timer. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + watchdog@802000040000 { + compatible = "marvell,octeontx2-wdt"; + reg = <0x00008020 0x00040000 0x00000000 0x00020000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>; + clocks = <&sclk>; + clock-names = "ref_clk"; + marvell,wdt-timer-index = <63>; + }; + }; + +... -- 2.17.1
