Re: [PATCH 2/2] arm64: dts: qcom: ipq9574: add few device nodes

[Kathiravan T <quic_kathirav@xxxxxxxxxxx>]

On 3/31/2023 1:45 AM, Sricharan Ramabadhran wrote:
> On 3/29/2023 11:07 AM, Kathiravan T wrote:
> > Add QUP(SPI / I2C) peripheral, PRNG, WDOG and the remaining UART nodes.
> > While at it, enable the SPI NOR in RDP433 board.
> >
> > Signed-off-by: Kathiravan T <quic_kathirav@xxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts |  21 ++
> >   arch/arm64/boot/dts/qcom/ipq9574.dtsi       | 202 ++++++++++++++++++++
> >   2 files changed, 223 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts 
> > b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> > index 2ce8e09e7565..7be578017bf7 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> > @@ -29,6 +29,20 @@
> >       status = "okay";
> >   };
> >   +&blsp1_spi0 {
> > +    pinctrl-0 = <&spi_0_pins>;
> > +    pinctrl-names = "default";
> > +    status = "okay";
> > +
> > +    flash@0 {
> > +        compatible = "micron,n25q128a11", "jedec,spi-nor";
> > +        reg = <0>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +        spi-max-frequency = <50000000>;
> > +    };
> > +};
> > +
> >   &sdhc_1 {
> >       pinctrl-0 = <&sdc_default_state>;
> >       pinctrl-names = "default";
> > @@ -77,6 +91,13 @@
> >               bias-pull-down;
> >           };
> >       };
> > +
> > +    spi_0_pins: spi-0-state {
> > +        pins = "gpio11", "gpio12", "gpio13", "gpio14";
> > +        function = "blsp0_spi";
> > +        drive-strength = <8>;
> > +        bias-disable;
> > +    };
> >   };
> >     &xo_board_clk {
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi 
> > b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > index 14a3396b0381..f3da0190284c 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > @@ -122,6 +122,13 @@
> >           #size-cells = <1>;
> >           ranges = <0 0 0 0xffffffff>;
> >   +        rng: rng@e3000 {
> > +            compatible = "qcom,prng-ee";
> > +            reg = <0x000e3000 0x1000>;
> > +            clocks = <&gcc GCC_PRNG_AHB_CLK>;
> > +            clock-names = "core";
> > +        };
> > +
> >           tlmm: pinctrl@1000000 {
> >               compatible = "qcom,ipq9574-tlmm";
> >               reg = <0x01000000 0x300000>;
> > @@ -184,6 +191,36 @@
> >               status = "disabled";
> >           };
> >   +        blsp_dma: dma-controller@7884000 {
> > +            compatible = "qcom,bam-v1.7.0";
> > +            reg = <0x07884000 0x2b000>;
>
>  Does the size needs to be 0x2b000 really ?


As per the document, BLSP DMA block size is 0x2b000, however the last 
register offset is 0x13934. In most of the places, irrespective of last 
register offset, we covered the entire region as mentioned in the document.


Thanks, Kathiravan T.


> Regards,
>  Sricharan