On 27/03/2023 17:35, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@xxxxxxxxxxx>
>
> For the Anbernic devices to display properly, we need to specify the
> clock frequency of the PLL_VPLL. Adding the parent clock in the
> rk356x.dtsi requires us to update our clock definitions to accomplish
> this.
>
> Fixes: 64b69474edf3 ("arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x")
>
> Signed-off-by: Chris Morgan <macromorgan@xxxxxxxxxxx>
No line breaks between tags.
Best regards,
Krzysztof
