On Mon, Mar 20, 2023 at 06:37:48PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@xxxxxxxx>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Tested-by: Tommaso Merciai <tomm.merciai@xxxxxxxxx>
> Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx>
> Co-developed-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
> Signed-off-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
> Co-developed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
> Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
> ---
> + S7_0: cpu@0 {
> + compatible = "sifive,s7", "riscv";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <8192>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <16384>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imac_zba_zbb";
> + tlb-split;
> + status = "disabled";
Jess pointed out on IRC that this S7 entry looks wrong as it is claiming
that the S7 has an mmu. I didn't go looking back in the history of
u74-mc core complex manuals, but the latest version does not show an mmu
for the S7.
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