On 23-03-15 18:44:09, Minda Chen wrote: > The dt-binding doc of Cadence USBSS-DRD controller wrapper > layer. > > Signed-off-by: Minda Chen <minda.chen@xxxxxxxxxxxxxxxx> Reviewed-by: Peter Chen <peter.chen@xxxxxxxxxx> > --- > .../bindings/usb/starfive,jh7110-usb.yaml | 119 ++++++++++++++++++ > 1 file changed, 119 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml > > diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml > new file mode 100644 > index 000000000000..b1a8dc6d7b4b > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml > @@ -0,0 +1,119 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller > + > +maintainers: > + - Minda Chen <minda.chen@xxxxxxxxxxxxxxxx> > + > +properties: > + compatible: > + const: starfive,jh7110-usb > + > + clocks: > + items: > + - description: lpm clock > + - description: stb clock > + - description: apb clock > + - description: axi clock > + - description: utmi apb clock > + > + clock-names: > + items: > + - const: lpm > + - const: stb > + - const: apb > + - const: axi > + - const: utmi_apb > + > + resets: > + items: > + - description: PWRUP reset > + - description: APB reset > + - description: AXI reset > + - description: UTMI_APB reset > + > + starfive,sys-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle to System Register Controller sys_syscon node. > + - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB. > + description: > + The phandle to System Register Controller syscon node and the offset > + of SYS_SYSCONSAIF__SYSCFG register for USB. > + > + starfive,stg-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle to System Register Controller stg_syscon node. > + - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for USB. > + - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for USB. > + - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for USB. > + - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for USB. > + description: > + The phandle to System Register Controller syscon node and the offset > + of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset > + for USB. > + > + "#address-cells": > + maximum: 2 > + > + "#size-cells": > + maximum: 2 > + > + ranges: true > + > +patternProperties: > + "^usb@[0-9a-f]+$": > + type: object > + > +required: > + - compatible > + - clocks > + - clock-names > + - resets > + - starfive,sys-syscon > + - starfive,stg-syscon > + - "#address-cells" > + - "#size-cells" > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + usb@10100000 { > + compatible = "starfive,jh7110-usb"; > + clocks = <&syscrg 4>, > + <&stgcrg 5>, > + <&stgcrg 1>, > + <&stgcrg 3>, > + <&stgcrg 2>; > + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; > + resets = <&stgcrg 10>, > + <&stgcrg 8>, > + <&stgcrg 7>, > + <&stgcrg 9>; > + starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>; > + starfive,sys-syscon = <&sys_syscon 0x18>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x10100000 0x100000>; > + > + usb@0 { > + compatible = "cdns,usb3"; > + reg = <0x0 0x10000>, > + <0x10000 0x10000>, > + <0x20000 0x10000>; > + reg-names = "otg", "xhci", "dev"; > + interrupts = <100>, <108>, <110>; > + interrupt-names = "host", "peripheral", "otg"; > + maximum-speed = "super-speed"; > + dr_mode = "host"; > + }; > + }; > -- > 2.17.1 > -- Thanks, Peter Chen
