On 23-03-15 18:44:11, Minda Chen wrote:
> USB Glue layer and Cadence USB subnode configuration,
> also includes USB and PCIe phy dts configuration.
>
> Signed-off-by: Minda Chen <minda.chen@xxxxxxxxxxxxxxxx>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 7 +++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 54 +++++++++++++++++++
> 2 files changed, 61 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index a132debb9b53..c64476aebc1a 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -236,3 +236,10 @@
> pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
> +
> +&usb0 {
> + status = "okay";
> + usbdrd_cdns3: usb@0 {
> + dr_mode = "peripheral";
> + };
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index f70a4ed47eb4..17722fd1be62 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -362,6 +362,60 @@
> status = "disabled";
> };
>
> + usb0: usb@10100000 {
> + compatible = "starfive,jh7110-usb";
> + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
> + <&stgcrg JH7110_STGCLK_USB0_STB>,
> + <&stgcrg JH7110_STGCLK_USB0_APB>,
> + <&stgcrg JH7110_STGCLK_USB0_AXI>,
> + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
> + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
> + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
> + <&stgcrg JH7110_STGRST_USB0_APB>,
> + <&stgcrg JH7110_STGRST_USB0_AXI>,
> + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
> + starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
> + starfive,sys-syscon = <&sys_syscon 0x18>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x10100000 0x100000>;
Why it is four entry at ranges? Your address-cells and size-cells are
both 1, and your binding-doc is also three?
Peter
> +
> + usbdrd_cdns3: usb@0 {
> + compatible = "cdns,usb3";
> + reg = <0x0 0x10000>,
> + <0x10000 0x10000>,
> + <0x20000 0x10000>;
> + reg-names = "otg", "xhci", "dev";
> + interrupts = <100>, <108>, <110>;
> + interrupt-names = "host", "peripheral", "otg";
> + phys = <&usbphy0>;
> + phy-names = "cdns3,usb2-phy";
> + maximum-speed = "super-speed";
> + };
> + };
> +
> + usbphy0: phy@10200000 {
> + compatible = "starfive,jh7110-usb-phy";
> + reg = <0x0 0x10200000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
> + <&stgcrg JH7110_STGCLK_USB0_APP_125>;
> + clock-names = "125m", "app_125";
> + #phy-cells = <0>;
> + };
> +
> + pciephy0: phy@10210000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10210000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> + pciephy1: phy@10220000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10220000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> stgcrg: clock-controller@10230000 {
> compatible = "starfive,jh7110-stgcrg";
> reg = <0x0 0x10230000 0x0 0x10000>;
> --
> 2.17.1
>
--
Thanks,
Peter Chen
