> RX delay = rx-delay-basic (0ns or 1.9ns) + x-delay-additional-ps > (N*150ps, N = 0 ~ 15) > If rx-delay-basic is removed and controlled by phy-mode. > when phy-mode is rgmii-id or rgmii-rxid, RX delay is 1.9ns + N*150ps. > But sometimes 1.9ns is still too big, we just need 0ns + N*150ps. > > For this case, can we do like following ? > rx-internal-delay-ps: > enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, > 1650, 1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800, > 2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ] > default: 0 > rx-internal-delay-ps is 0ns + N*150ps and 1.9ns + N*150ps. > And check whether need rx-delay-basic (1.9ns) by the val of > rx-internal-delay-ps? Nothing says delays are only positive. So you could have rgmii-id or rgmii-rxid and a rx-internal-delay-ps of -150, if you need less than 1.9ns. As i said, rx-internal-delay-ps is used to fine tune the delay. > We can't reduce this down to tx-clk-inverted. > There are two mac and two yt8531 on their board. Each of yt8531 need > different config in DTS. They need adjust tx clk delay in > link_change_notify callback function according to current speed. > > They configured tx-clk-xxxx-inverted like this : > > speed GMAC0 GMAC1 > 1000M 1 0 tx-clk-1000-inverted > 100M 1 1 tx-clk-100-inverted > 10M 0/1 0/1 tx-clk-10-inverted What MAC is this? It seems very oddly designed, getting close to broken. I've not seen any other MAC/PHY combination need anything like this. > Can we put tx-clk-adj-enabled, tx-clk-10-inverted, tx-clk-100-inverted > and tx-clk-1000-inverted in tx-clk-10-inverted like bit in byte? No, they are individual boolean properties, so should be kept as they are. But i really think somebody should be looking deep into the MAC design to understand why it is like this, and if the MAC can sort out this mess itself. Andrew
