On Fri, Jan 06, 2023 at 01:01:52AM +0000, Andre Przywara wrote: > The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical > die as their R528/T113-s siblings with ARM Cortex-A7 cores. > > To allow sharing the basic SoC .dtsi files across those two > architectures as well, introduce a symlink to the RISC-V DT directory. Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Thanks, Conor. > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> > --- > scripts/dtc/include-prefixes/riscv | 1 + > 1 file changed, 1 insertion(+) > create mode 120000 scripts/dtc/include-prefixes/riscv > > diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv > new file mode 120000 > index 0000000000000..2025094189380 > --- /dev/null > +++ b/scripts/dtc/include-prefixes/riscv > @@ -0,0 +1 @@ > +../../../arch/riscv/boot/dts > \ No newline at end of file > -- > 2.35.5 > >
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