Corstone500[0] is a platform from arm, which includes Cortex-A cores and ideal starting point for feature rich System on Chip (SoC) designs based on the Cortex-A5 core. These device trees contains the necessary bits to support the Corstone 500 FVP (Fixed Virtual Platform) and the FPGA MPS3 board. 0: https://developer.arm.com/documentation/102262/0000 Signed-off-by: Emekcan Aras <emekcan.aras@xxxxxxx> --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/corstone500.dts | 182 ++++++++++++++++++++++++++++++ 2 files changed, 184 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/corstone500.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6aa7dc4db2fc..4dc4df0707dc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1465,7 +1465,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \ vexpress-v2p-ca5s.dtb \ vexpress-v2p-ca9.dtb \ vexpress-v2p-ca15-tc1.dtb \ - vexpress-v2p-ca15_a7.dtb + vexpress-v2p-ca15_a7.dtb \ + corstone500.dtb dtb-$(CONFIG_ARCH_VIRT) += \ xenvm-4.2.dtb dtb-$(CONFIG_ARCH_VT8500) += \ diff --git a/arch/arm/boot/dts/corstone500.dts b/arch/arm/boot/dts/corstone500.dts new file mode 100644 index 000000000000..bcca7d736c85 --- /dev/null +++ b/arch/arm/boot/dts/corstone500.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + */ + + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "ARM Corstone500"; + compatible = "arm,corstone500"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_on = <0x84000003>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "psci"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x7f000000>; + }; + + L2: cache-controller@1c010000 { + compatible = "arm,pl310-cache"; + reg = <0x1c010000 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + cache-level = <2>; + cache-unified; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + refclk7500khz: clock-refclk7500khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <7500000>; + clock-output-names = "apb_pclk"; + }; + + refclk24mhz: clock-refclk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: clock-refclk24mhzx2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + + gic: interrupt-controller@1c001000 { + compatible = "arm,cortex-a5-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c001000 0x1000>, + <0x1c000100 0x100>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc{ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + clock_frequency = <50000000>; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@1a200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a200000 0x1000>; + interrupts = <GIC_SPI 8 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&refclk7500khz>; + clock-names = "apb_pclk"; + }; + + uart1: serial@1a210000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a210000 0x1000>; + interrupts = <GIC_SPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&refclk7500khz>; + clock-names = "apb_pclk"; + }; + + timer0: timer@1a040000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a040000 0x1000>; + clock-frequency = <7500000>; + + frame@1a050000 { + frame-number = <0>; + interrupts = <GIC_SPI 2 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1a050000 0x1000>; + }; + }; + + smsc: ethernet@4020000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x40200000 0x10000>; + interrupts = <GIC_SPI 43 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + reg-io-width = <4>; + phy-mode = "mii"; + smsc,irq-active-high; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + rtc@1a220000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x1a220000 0x1000>; + clocks = <&refclk24mhz>; + interrupts = <GIC_SPI 6 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + clock-names = "apb_pclk"; + }; + }; + + v2m_fixed_3v3: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; -- 2.25.1
