Add bindings to describe implementation of the ARM Corstone500 platform. Signed-off-by: Emekcan Aras <emekcan.aras@xxxxxxx> --- .../bindings/arm/arm,corstone500.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone500.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,corstone500.yaml b/Documentation/devicetree/bindings/arm/arm,corstone500.yaml new file mode 100644 index 000000000000..cfe41f7760fd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,corstone500.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,corstone500.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Corstone500 + +maintainers: + - Emekcan Aras <emekcan.aras@xxxxxxx> + - Rui Miguel Silva <rui.silva@xxxxxxxxxx> + +description: |+ + Corstone-500 is an ideal starting point for feature rich System on Chip + (SoC) designs based on the Cortex-A5 core. These designs can be used in + Internet of Things (IoT) and embedded products. + + Corstone-500 includes most of the Arm IP in the SSE-500 subsystem and + example integration layer, an FPGA, and access to modelling options. + +properties: + $nodename: + const: '/' + compatible: + items: + - const: arm,corstone500 + +additionalProperties: true + +... -- 2.25.1
